Field of the Invention
The present invention relates to integrated circuits (ICs) and, more specifically but not exclusively, to built-in self-test (BIST) techniques for IC memory.
Description of the Related Art
This section introduces aspects that may help facilitate a better understanding of the invention. Accordingly, the statements of this section are to be read in this light and are not to be understood as admissions about what is prior art or what is not prior art.
There are a variety of memory BIST (built-in self-test) approaches for field-programmable gate arrays (FPGAs) that use fabric resources to test embedded memories at their rated frequency of operation. One drawback of these approaches is that they rely on software-programmable routing resources in the FPGA fabric and often do not achieve worst-case stress conditions for minimum-delay paths due to latencies in the fabric routing. This might lead to defective parts being shipped to customers and consequent customer returns. For example, one possible defect relates to a hold-time issue in an input register within an embedded RAM (random-access memory) block.
Another disadvantage of using fabric-based BIST testing to test FPGA embedded memory at-speed is the resource utilization on the FPGA. (As used herein, the term “at-speed” refers to the normal configuration clock frequency of the device being tested.) Since the fabric may be used to build BIST engines for hundreds of different blocks of embedded memory, the multiple BIST masters create a lot of congestion for the place-and-route tool, thereby resulting in a lower-speed design, which defeats the purpose of the test. Limiting the number of BIST masters would add delay to the programmable routes from those masters to the embedded memory blocks, thereby resulting once again in a lower-speed design.